This application is based on Japanese Patent Applications No. 9-234285, filed on Aug. 29, 1997 and No. 9-116861, filed on May 7, 1997 the contents of which are cited herein by reference.
The present invention relates to an interrupt control process for a computer system and, more particularly, to respective parallel processes during the interrupt control process.
In recent years, various laptop and notebook portable personal computers which can be operated by batteries have been developed. Generally in an initialization process of a personal computer, a memory and various I/O devices mounted on the computer are sequentially initialized. For example, in a notebook personal computer, the initialization process is executed by the following procedure in accordance with the POST routine of the BIOS, as shown in FIG. 1.
(1) Initialize Memory and Chip Set (step S100) PA1 (2) Initialize Keyboard Controller (KBC) and Internal/External Keyboard (step S110) PA1 (3) Initialize Display Controller and Detect External CRT (step S120) PA1 (4) Initialize Hard Disk (step S130) PA1 (5) Initialize Optional Device (step S140) PA1 (1) Panel Light Off Sequence Process (S200) PA1 (2) HDD Motor Off Sequence Process (S210) PA1 (3) Saving Sequence Process of Various I/O Device Registers (S220) PA1 (4) Memory Check Sum (S230) PA1 (5) Rewrite of Flash ROM (S240)
In initializing respective devices such as the keyboard controller, the display controller, and the hard disk, commands are frequently issued from the PST routine to the devices. The device receiving a command requires a given time to complete a process corresponding to the command. Every time the POST routine issues a command, it polls a device to which the command is issued, and checks whether the device completes the command process. After confirming the completion of the command process, the POST routine issues the next command to the device.
In this manner, in initializing each device, the issuing timing of the next command is delayed by a time necessary for the command process of the device. During this wait time, the POST routine can originally initialize another device.
In the conventional system, however, since a plurality of devices are sequentially initialized, the wait time in the initialization process of each device cannot be effectively used. The time required to initialize the entire system is therefore the sum of times (including wait times) necessary to initialize respective devices mounted on the system. The initialization process of the computer requires a long time.
Further, an interrupt control process of such a personal computer such as a rapid resume/suspend process of saving the current operation environment and returning the operation environment at the next start of the computer system or a docking/undocking process of connecting/disconnecting a docking station or an external device corresponding to a device bay during the energization of the computer system is executed as an interrupt control process during the operation of an operation system (to be referred to as an OS hereinafter).
According to the procedure of the conventional interrupt control process, when a power supply microcomputer incorporated in the computer system detects depression of a power supply switch, the power supply microcomputer issues an interrupt request to an interrupt control logic via an interrupt request line. Similarly, if a docking station and an extension device are respectively docked to the extension bus connector of the computer system main body and the device bay during the operation of the OS, each circuit for controlling the docking issues an interrupt request to the interrupt control logic.
Upon reception of the interrupt request, the interrupt control logic issues a system management interrupt (to be referred to as an SMI hereinafter) to a central processing unit (to be referred to as a CPU hereinafter).
When the CPU receives the SMI signal, the CPU operation mode shifts to a system management mode (to be referred to as an SMM hereinafter) to start an interrupt control process stored in the BIOS-ROM. The interrupt control process executes an interrupt control process corresponding to the interrupt signal requested from the CPU.
In a CPU available from Intel Corp., U.S.A., the SMM means a CPU operation mode set in shift of the CPU to the interrupt control process in the BIOS-ROM when an SMI# signal is input from the computer system to the CPU.
While the CPU is in the SMM, no computer system can request a new interrupt (e.g., IRQ, INTR, or SMI) from the CPU. The interrupt control process must directly execute a series of processes. When a time wait is required for a predetermined command process issued to various I/O devices, another process in the interrupt control process cannot be executed, and the process must wait a certain time.
A rapid suspend process will be described as an example of the interrupt control process with reference to FIG. 2. The rapid suspend process is made up of the following five processes.
In sequence processes (1) through (3), a certain time is required for various I/O devices receiving commands to complete processes corresponding to the commands. The next sequence cannot be executed until each sequence process is completed.
In each sequence process, the timing of the next sequence process is delayed by a time necessary for the command process of the device. The time required to execute the interrupt control process (rapid suspend process) of the system using the SMM is as long as the sum of times (including wait times) corresponding to the commands of respective sequence processes.
To accept a power on/off request from an I/O device (power supply microcomputer) of the computer system during the rapid suspend process, the presence/absence of the request from the power supply microcomputer is checked by polling (S250) during the rapid suspend process, so the process cannot be performed timely.
As described above, in the conventional system, when the interrupt control process is to be executed during the SMM, another interrupt request cannot be accepted, so the interrupt control process is time-consuming.
Since no interrupt request from another I/O device can be accepted during the interrupt control process, a special process of polling various I/O devices and checking the presence/absence of a request must be performed.
As described above, in the conventional system, only two, specific and another devices can be initialized parallel. In a system configuration in which a plurality of devices require wait periods for their initialization operations, the initialization time is difficult to satisfactorily shorten.